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FEATURES
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LTC2460/LTC2462 Ultra-Tiny, 16-Bit ADCs with 10ppm/C Max Precision Reference DESCRIPTION
The LTC(R)2460/LTC2462 are ultra tiny, 16-Bit analog-todigital converters with an integrated precision reference. They use a single 2.7V to 5.5V supply and communicate through an SPI Interface. The LTC2460 is single-ended with a 0V to VREF input range and the LTC2462 is differential with a VREF input range. Both ADC's include a 1.25V integrated reference with 2ppm/C drift performance and 0.1% initial accuracy. The converters are available in a 12-pin DFN 3mm x 3mm package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The LTC2460/LTC2462 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. Following a single conversion, the LTC2460/LTC2462 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA. The LTC2460/LTC2462 can sample at 60 conversions per second, and due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. Both include continuous internal offset and fullscale calibration algorithms which are transparent to the user, ensuring accuracy over time and the operating temperature range.
16-Bit Resolution, No Missing Codes Internal Reference, High Accuracy 10ppm/C (Max) Single-Ended (LTC2460) or Differential (LTC2462) 2LSB Offset Error 0.01% Gain Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 1.5mA Supply Current 2A (Max) Sleep Current Internal Oscillator--No External Components Required SPI Interface Ultra-Tiny 12-Lead 3mm x 3mm DFN and MSOP Packages
APPLICATIONS
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System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
2.7V TO 5.5V REFERENCE OUTPUT VOLTAGE (V) 1.2520 1.2515 1.2510 1.2505 1.2500 1.2495 1.2490 1.2485 1.2480 -50 0.1F 0.1F IN
+
VREF vs Temperature
0.1F REFOUT COMP VCC SCK LTC2462 IN- SDO CS REF- GND
0.1F
10F
10k
10k
SPI INTERFACE
10k
0.1F R
24602 TA01a
-30
-10 10 30 50 TEMPERATURE (C)
70
90
24602 TA01b
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LTC2460/LTC2462 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... -0.3V to 6V Analog Input Voltage (IN+, IN-, IN, REF-, COMP REFOUT) ............................ -0.3V to (VCC + 0.3V) , Digital Voltage (VSDI, VSDO, VSCK, VCS) ................. -0.3V to (VCC + 0.3V)
Storage Temperature Range................... -65C to 150C Operating Temperature Range LTC2460C/LTC2462C ............................... 0C to 70C LTC2460I/LTC2462I.............................. -40C to 85C
PIN CONFIGURATION
LTC2462 TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 VCC 11 GND 10 IN- 9 IN+ 8 REF- 7 GND REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7 VCC GND IN- IN+ REF- GND LTC2462
DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL LTC2460 TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 VCC 11 GND 10 GND 9 IN 8 REF- 7 GND LTC2460
MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND GND IN REF- GND
DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL
MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
ORDER INFORMATION
LEAD FREE FINISH LTC2460CDD#PBF LTC2460IDD#PBF LTC2460CMS#PBF LTC2460IMS#PBF LTC2462CDD#PBF LTC2462IDD#PBF LTC2462CMS#PBF LTC2462IMS#PBF TAPE AND REEL LTC2460CDD#TRPBF LTC2460IDD#TRPBF LTC2460CMS#TRPBF LTC2460IMS#TRPBF LTC2462CDD#TRPBF LTC2462IDD#TRPBF LTC2462CMS#TRPBF LTC2462IMS#TRPBF PART MARKING* LFDQ LFDQ 2460 2460 LDXM LDXM 2462 2462 PACKAGE DESCRIPTION 12-Lead Plastic (3mm x 3mm) DFN 12-Lead Plastic (3mm x 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 12-Lead Plastic (3mm x 3mm) DFN 12-Lead Plastic (3mm x 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2460/LTC2462 ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Includes Contributions of ADC and Internal Reference Includes Contributions of ADC and Internal Reference C-Grade I-Grade
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS (Note 3) (Note 4)
l l l
MIN 16
TYP 1 2 0.02 0.01 2 5 2.2 80
MAX 10 10 0.25 10
UNITS Bits LSB LSB LSB/C % of FS ppm/C ppm/C VRMS dB
Transition Noise Power Supply Rejection DC
ANALOG INPUTS
specifications are at TA = 25C.
PARAMETER SYMBOL VIN+ VIN VIN VOR+, VUR+ VOR-, VUR- CIN IDC_LEAK(IN+, IN-, IN) IDC_LEAK(IN-) ICONV VREF
-
The l denotes the specifications which apply over the full operating temperature range, otherwise
CONDITIONS LTC2462 LTC2462 LTC2460 VIN- = 0.625V (See Figure 3) VIN+ = 0.625V (See Figure 3) VIN = GND (Note 8) VIN = VCC (Note 8) VIN = GND (Note 8) VIN = VCC (Note 8)
l l l l l l l l
MIN 0 0 0
TYP
MAX VREF VREF VREF
UNITS V V V LSB LSB pF
Positive Input Voltage Range Negative Input Voltage Range Input Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN- IN+, IN-, IN Sampling Capacitance IN+, IN- DC Leakage Current (LTC2462) IN DC Leakage Current (LTC2460) IN- DC Leakage Current Input Sampling Current (Note 5) Reference Output Voltage Reference Voltage Coefficient
8 8 0.35 -10 -10 -10 -10 1.247 1 1 1 1 50 1.25 2 5 -90
l l
10 10 10 10 1.253 10
nA nA nA nA nA V ppm/C ppm/C dB mA A mV/mA nV/Hz
(Note 11) C-Grade I-Grade 2.7V VCC 5.5V VCC = 5.5, Forcing Output to GND VCC = 5.5, Forcing Output to GND 2.7V VCC 5.5V, IOUT = 100A Sourcing , , CCOMP= 0.1F CREFOUT = 0.1F At f = 1kHz
l
Reference Line Regulation Reference Short Circuit Current COMP Pin Short Circuit Current Reference Load Regulation Reference Output Noise Density
35 200 3.5 30
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Nap Sleep CONDITIONS
l l l l
POWER REQUIREMENTS
MIN 2.7
TYP
MAX 5.5
UNITS V mA A A
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1.5 800 0.2
2.5 1500 2
3
LTC2460/LTC2462
The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25C. (Note 2)
SYMBOL VIH VIL IIN CIN VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current IO = -800A IO = 1.6mA
l l l
DIGITAL INPUTS AND DIGITAL OUTPUTS
CONDITIONS
MIN
l l l
TYP
MAX 0.3
UNITS V V A pF V
VCC - 0.3 -10 10 VCC - 0.5 0.4 -10 10 10
V A
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25C.
SYMBOL tCONV fSCK tlSCK thSCK t1 t2 t3 tKQ t4 t5 PARAMETER Conversion Time SCK Frequency Range SCK Low Period SCK High Period CS Falling Edge to SDO Low Z CS Rising Edge to SDO High Z CS Falling Edge to SCK Falling Edge SCK Falling Edge to SDO Valid SDI Setup Before SCK SDI Hold After SCK (Note 7) (Note 3) (Note 3) (Notes 7, 8) (Notes 7, 8) CONDITIONS
l l l l l l l l l l
MIN 13 250 250 0 0 100 0 100 100
TYP 16.6
MAX 23 2
UNITS ms MHz ns ns
100 100 100
ns ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = VREF VIN = VIN+ - VIN-, -VREF VIN VREF; VINCM = (VIN+ + VIN-)/2. Note 3. Guaranteed by design, not subject to test. Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation. Note 5: CS = VCC. A positive current is flowing into the DUT pin. Note 6: SCK = VCC or GND. SDO is high impedance. Note 7: See Figure 4. Note 8: See Figure 5. Note 9: Input sampling current is the average input current drawn from the input sampling network while the LTC2460/LTC2462 is actively sampling the input. Note 10: A positive current is flowing into the DUT pin. Note 11: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.
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LTC2460/LTC2462 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
3 2 1 INL (LSB) INL (LSB) 0 -1 -2 -3 -1.25 VCC = 5.5V TA = -45C, 25C, 90C 3 2 1 0 -1 -2 -3 -1.25 INL (LSB)
(TA = 25C, unless otherwise noted)
Integral Nonlinearity
VCC = 2.7V TA = -45C, 25C, 90C 3 2 1 0 -1 -2
Maximum INL vs Temperature
VCC = 5.5V, 4.1V, 2.7V
0.25 0.75 -0.75 -0.25 DIFFERENTIAL INPUT VOLTAGE (V)
1.25
0.25 0.75 -0.75 -0.25 DIFFERENTIAL INPUT VOLTAGE (V)
1.25
-3 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
24602 G03
24602 G01
24602 G02
Offset Error vs Temperature
5 4 3 OFFSET ERROR (LSB) 2 1 0 -1 -2 -3 -4 -5 -50 -30 50 -10 10 30 TEMPERATURE (C) 70 90 VCC = 2.7V VCC = 4.1V VCC = 5.5V ADC GAIN ERROR (LSB) 25
ADC Gain Error vs Temperature
10 VCC = 5.5V 20 TRANSITION NOISE RMS (V) 9 8 7 6 5 4 3 2 1 75 100
24602 G05
Transition Noise vs Temperature
15
10
VCC = 4.1V
VCC = 2.7V
5 VCC = 2.7V 0 -50
VCC = 5.5V
-25
0 25 50 TEMPERATURE (C)
0 -50
-30
50 -10 10 30 TEMPERATURE (C)
70
90
24602 G04
24602 G06
Conversion Mode Power Supply Current vs Temperature
2.0 1.9 CONVERSION CURRENT (mA) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -50 -30 50 -10 10 30 TEMPERATURE (C) 70 90 50 VCC = 2.7V SLEEP CURRENT (nA) VCC = 5.5V VCC = 4.1V 350 300 250 200 150
Sleep Mode Power Supply Current vs Temperature
1.2508 REFERENCE OUTPUT VOLTAGE (V) 1.2507 1.2506 1.2505 1.2504 1.2503
VREF vs Temperature
VCC = 5.5V
VCC = 4.1V 100 VCC = 2.7V -30 50 -10 10 30 TEMPERATURE (C) 70 90
0 -50
1.2502 -50
-30
50 -10 10 30 TEMPERATURE (C)
70
90
24602 G07
24602 G08
24602 G09
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LTC2460/LTC2462 TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Rejection vs Frequency at VCC
0 -20 CONVERSION TIME (ms) REJECTION (dB) -40 -60 -80 21 20 19 18 17 16 15 14 -50 VREF (V) VCC = 5V, 4.1V, 3V
(TA = 25C, unless otherwise noted)
Conversion Time vs Temperature
1.24892 1.24891 1.24890 1.24889 1.24888 1.24887 1.24886 1.24885 -25 25 50 0 TEMPERATURE (C) 75 100
24602 G11
VREF vs VCC
TA = 25C
-100 -120
1
10
100 1k 10k 100k FREQUENCY AT VCC (Hz)
1M
10M
1.24884 2.0
2.5
3.0
3.5
24602 G10
4.0 4.5 VCC (V)
5.0
5.5
6.0
24602 G12
PIN FUNCTIONS
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, this voltage sets the fullscale input range of the ADC. For noise and reference stability connect to a 0.1F capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT cannot be overdriven by an external reference. For applications that require an input range greater than 0V to 1.25V, please refer to the LTC2450/ LTC2452. COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1F capacitor to GND. CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO output. A HIGH on this pin places the SDO output pin in a high impedance state and any inputs on SDI and SCK will be ignored. SDI (Pin 4): Serial Data Input Pin. This pin is used to program the sleep mode and 30Hz/60Hz output rate (LTC2460). SCK (Pin 5): Serial Clock Input. SCK synchronizes the serial data input/output. Once the conversion is complete, a new data bit is produced at the SDO pin following each SCK falling edge. Data is shifted into the SDI pin on each rising edge of SCK. SDO (Pin 6): Three-State Serial Data Output. SDO is used for serial data output during the DATA INPUT/OUTPUT state and can be used to monitor the conversion status. GND (Pins 7, 11): Ground. Connect directly to the ground plane through a low impedance connection. REF- (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor. IN+ (LTC2462), IN (LTC2460) (Pin 9): Positive input voltage for the LTC2462 differential device. ADC input for the LTC2460 single-ended device. IN- (LTC2462), GND (LTC2460) (Pin 10): Negative input voltage for the LTC2462 differential device. GND for the LTC2460 single-ended device. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10F capacitor in parallel with a low-series-inductance 0.1F capacitor located as close to the device as possible. Exposed Pad (Pin 13 - DFN Package): Ground. Connect directly to the ground plane through a low impedance connection.
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LTC2460/LTC2462 BLOCK DIAGRAM
1 REFOUT 2 COMP 12 VCC CS SPI INTERFACE SCK SDO 3 5 6 4
9
IN+ (IN)
A/D CONVERTER
INTERNAL REFERENCE
-
10 IN- (GND) A/D CONVERTER
DECIMATING SINC FILTER
SDI
INTERNAL OSCILLATOR REF- 7,11,13 (DD PACKAGE) GND
24602 BD
8
( ) PARENTHESIS INDICATE LTC2460
Figure 1. Functional Block Diagram
APPLICATIONS INFORMATION
CONVERTER OPERATION Converter Operation Cycle The LTC2460/LTC2462 are low power, delta sigma, analog to digital converters with a simple SPI interface (see Figure 1). The LTC2462 has a fully differential input while the LTC2460 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT, SLEEP/NAP and DATA INPUT/OUTPUT. , The operation begins with the CONVERT state (see Figure 2). Once the conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read or an abort is initiated the device begins a new conversion. The CONVERT state duration is determined by the LTC2460/ LTC2462 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2460/LTC2462 enters the SLEEP/NAP state and remains there until the chip select is LOW (CS = LOW). Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state.
POWER-ON RESET CONVERT
SLEEP/NAP
NO
CS = LOW?
YES
DATA INPUT/OUTPUT
NO
16TH FALLING EDGE OF SCK OR CS = HIGH?
YES
24602 F02
Figure 2. LTC2460/LTC2462 State Transition Diagram
While in the SLEEP/NAP state, when chip select input is HIGH (CS = HIGH), the LTC2460/LTC2462's converters are powered down. This reduces the supply current by approximately 50%. While in the Nap state the reference remains powered up. In order to power down the reference in addition to the converter, the user can select the SLEEP
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LTC2460/LTC2462 APPLICATIONS INFORMATION
mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, the SLEEP state is entered and power is reduced to less than 2A. The reference is powered up once CS is brought low. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1F). Upon entering the DATA INPUT/OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin. During the DATA INPUT/OUTPUT state, the LTC2460/ LTC2462 can be programmed to SLEEP or NAP (default) following the next conversion cycle. Data is shifted into the device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second bit EN2 = 0 the device is enabled for programming. The following two bits (SPD and SLP) will be written into the device. SPD (only used for the LTC2460) to select the 60Hz output rate, no offset calibration mode (SPD = 0, default). Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the LTC2462. The next bit (SLP) enables the sleep or nap mode. If SLP = 0 (default) the reference remains powered up at the end of the next conversion
20 16 12 8 OUTPUT CODE 4 0 -4 -8 -12 -16 -20 -0.001 -0.005 0.005 0 VIN+/VREF+ 0.001 0.0015
24602 F03
cycle. If SLP = 1, the reference powers down following the next conversion cycle. The remaining 12 SDI input bits are ignored (don't care). SDI may also be tied directly to GND or VDD in order to simplify the user interface. In the case of the LTC2460, the 60Hz output rate is selected if SDI is tied low and the 30Hz output rate is selected if SDI is tied to VDD. The LTC2462 output rate is always 60Hz independent of SDI or SPD. The reference sleep mode is disabled for both the LTC2460 and LTC2462 if SDI is tied to GND or VDD. The DATA INPUT/OUTPUT state concludes in one of two different ways. First, the DATA INPUT/OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA INPUT/OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2460/LTC2462 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2460/LTC2462 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1F). The first conversion following powerup will be invalid since the reference voltage has not completely settled. The first conversion following power up can be discarded using the data abort command or simply read and ignored. The following conversions are accurate to the device specifications. Ease of Use The LTC2460/LTC2462 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore,
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SIGNALS BELOW GND
Figure 3. Output Code vs VIN+ with VIN- = 0 (LTC2462)
8
LTC2460/LTC2462 APPLICATIONS INFORMATION
multiplexing multiple analog input voltages requires no special actions. The LTC2460/LTC2462 perform offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2460/LTC2462 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks to interface directly to the LTC2460/LTC2462. Since the average input sampling current is 50nA, an external RC lowpass filter using 1k and 0.1F results in <1LSB additional error. Additionally, there is negligible leakage current between IN+ and IN-. Input Voltage Range (LTC2460) Ignoring offset and full-scale errors, the LTC2460 will theoretically output an "all zero" digital result when the input is at ground (a zero scale input) and an "all one" digital result when the input is at VREF (VREFOUT = 1.25V). In an under-range condition, for all input voltages below zero scale, the converter will generate the output code 0. In an over-range condition, for all input voltages greater than VREF, the converter will generate the output code 65535. For applications that require an input range greater than 0V to 1.25V, please refer to the LTC2450.
t3 t1 CS
Input Voltage Range (LTC2462) As mentioned in the Output Data Format section, the output code is given as 32768 * (VIN+ - VIN-)/VREF + 32768. For (VIN+ - VIN-) VREF, the output code is clamped at 65535 (all ones). For (VIN+ - VIN-) -VREF, the output code is clamped at 0 (all zeroes). The LTC2462 includes a proprietary architecture that can, typically, digitize each input up to 8 LSBs above VREF and below GND, if the differential input is within VREF. As an example (Figure 3), if the user desires to measure a signal slightly below ground, the user could set VIN- = GND, and VREF = 1.25V. If VIN+ = GND, the output code would be approximately 32768. If VIN+ = GND - 8LSB = -0.305mV, the output code would be approximately 32760. For applications that require an input range greater than 1.25V, please refer to the LTC2452. Output Data Format The LTC2460/LTC2462 generates a 16-bit direct binary encoded result. It is provided as a 16-bit serial stream through the SDO output pin under the control of the SCK input pin (see Figure 4). The LTC2462 (differential input) output code is given by 32768 * (VIN+ - VIN-)/VREF + 32768. The first bit output by the LTC2462, D15, is the MSB, which is 1 for VIN+ VIN- and 0 for VIN+ < VIN-. This bit is followed by successively less significant bits (D14, D13, ...) until the LSB is output by the LTC2462, see Table 1.
t2
D15 SDO MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
SCK tKQ EN1 SDI t5 t6 *SPD IS A DON'T CARE BIT FOR THE LTC2462 EN2 tlSCK SPD* SLP DON'T CARE
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thSCK
Figure 4. Data Input/Output Timing
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LTC2460/LTC2462 APPLICATIONS INFORMATION
Table 1. LTC2460/LTC2462 Output Data Format
SINGLE ENDED INPUT VIN (LTC2460) VREF VREF - 1LSB 0.75 * VREF 0.75 * VREF - 1LSB 0.5 * VREF 0.5 * VREF - 1LSB 0.25 * VREF 0.25 * VREF - 1LSB 0 DIFFERENTIAL INPUT VOLTAGE VIN+ - VIN- (LTC2462) VREF VREF - 1LSB 0.5 * VREF 0.5 * VREF - 1LSB 0 -1LSB -0.5 * VREF -0.5 * VREF - 1LSB -VREF D15 (MSB) 1 1 1 1 1 0 0 0 0 D14 1 1 1 0 0 1 1 0 0 D13 1 1 0 1 0 1 0 1 0 D12...D2 1 1 0 1 0 1 0 1 0 D1 1 1 0 1 0 1 0 1 0 D0 (LSB) 1 0 0 1 0 1 0 1 0 CORRESPONDING DECIMAL VALUE 65535 65534 49152 49151 32768 32767 16384 16383 0
The LTC2460 (single-ended input) output code is a direct binary encoded result, see Table 1. During the data output operation the CS input pin must be pulled low (CS = LOW). The data output process starts with the most significant bit of the result being present at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin after each falling edge detected at the SCK input pin. The output data can be reliably latched on the rising edge of SCK. Data Input Format The data input word is 4 bits long and consists of two enable bits (EN1 and EN2) and two programming bits (SPD and SLP). EN1 is applied to the first rising edge of SCK after the conversion is complete. Programming is enabled by setting EN1 = 1 and EN2 = 0. The speed bit (SPD) is only used by the LTC2460. In the default mode, SPD = 0, the output rate is 60Hz and continuous background offset calibration is not performed. By changing the SPD bit to 1, background offset calibration is performed and the output rate is reduced to 30Hz. Alternatively, SDI can be tied directly to ground (SPD = 0) or VCC (SPD = 1), eliminating the need to program the device. The LTC2462 data output rate is always 60Hz and background offset calibration is performed (SPD = don't care). The sleep bit (SLP) is used to power down the on chip reference. In the default mode, the reference remains powered up even when the ADC is powered down. If the SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered down until CS is pulled low. The reference startup time is approximately 12ms. In order to ensure a stable reference for the following conversions, either the data input/output time should be delayed 12ms after CS goes low or the first conversion following a reference start up should be discarded. If SDI is tied HIGH (LTC2460 operating in 30Hz mode) the SLP mode is disabled. Conversion Status Monitor For certain applications, the user may wish to monitor the LTC2460/LTC2462 conversion status. This can be achieved by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low (CS = LOW), the SDO output pin will provide an indication of the conversion status. SDO = HIGH is an indication of a conversion cycle in progress while SDO = LOW is an indication of a completed conversion cycle. An example of such a sequence is shown in Figure 5. Conversion status monitoring, while possible, is not required for the LTC2460/LTC2462 as its conversion time is fixed and typically 16.6ms (23ms maximum). Therefore, external timing can be used to determine the completion of a conversion cycle. SERIAL INTERFACE The LTC2460/LTC2462 transmit the conversion result and receive the start of conversion command through a synchronous 2-, 3- or 4-wire interface. This interface
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LTC2460/LTC2462 APPLICATIONS INFORMATION
t1 CS t2
SDO
SDI = LOW
SCK = HIGH
CONVERT
NAP
24602 F05
Figure 5. Conversion Status Monitoring Mode
can be used during the CONVERT and SLEEP states to assess the conversion status and during the DATA OUTPUT state to read the conversion result, and to trigger a new conversion. Serial Interface Operation Modes The modes of operation can be summarized as follows: 1) The LTC2460/LTC2462 function with SCK idle high (commonly known as CPOL = 1) or idle low (commonly known as CPOL = 0). 2) After the 16th bit is read, a new conversion is started if CS is pulled high or SCK is pulled low. 3) At any time during the Data Output state, pulling CS high causes the part to leave the I/O state, abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conversion status by pulling CS low and watching for SDO to go low. This feature is available only in the idle-high (CPOL = 1) mode. Serial Clock Idle-High (CPOL = 1) Examples In Figure 6, following a conversion cycle the LTC2460/ LTC2462 automatically enter the NAP mode with the ADC powered down. The ADC's reference will power down if the SLP bit was set high prior to the just completed conversion and CS is HIGH. Once CS goes low, the device powers up. The user can monitor the conversion status at convenient intervals using CS and SDO. Pulling CS LOW while SCK is HIGH tests whether or not the chip is in the CONVERT state. While in the CONVERT state, SDO is HIGH while CS is LOW. Once the conversion is complete, SDO is LOW
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD clk4 SLP DATA OUTPUT CONVERT
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clk15
clk16
SDI
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example. The Rising Edge of CS Starts a New Conversion
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LTC2460/LTC2462 APPLICATIONS INFORMATION
while CS is LOW. These tests are not required operational steps but may be useful for some applications. When the data is available, the user applies 16 clock cycles to transfer the result. The CS rising edge is then used to initiate a new conversion. The operation example of Figure 7 is identical to that of Figure 6, except the new conversion cycle is triggered by the falling edge of the serial clock (SCK). Serial Clock Idle-Low (CPOL = 0) Examples In Figure 8, following a conversion cycle the LTC2460/ LTC2462 automatically enters the NAP state. The device reference will power down if the SLP bit was set high prior to the just completed conversion and CS is HIGH. Once CS goes low, the reference powers up. The user determines data availability (and the end of conversion) based upon external timing. The user then pulls CS low (CS = ) and uses 16 clock cycles to transfer the result. Following the 16th rising edge of the clock, CS is pulled high (CS = ), which triggers a new conversion.
CS
The timing diagram in Figure 9 is identical to that of Figure 8, except in this case a new conversion is triggered by SCK. The 16th SCK falling edge triggers a new conversion cycle and the CS signal is subsequently pulled high. Examples of Aborting Cycle using CS For some applications, the user may wish to abort the I/O cycle and begin a new conversion. If the LTC2460/LTC2462 are in the data output state, a CS rising edge clears the remaining data bits from the output register, aborts the output cycle and triggers a new conversion. Figure 10 shows an example of aborting an I/O with idle-high (CPOL = 1) and Figure 11 shows an example of aborting an I/O with idle-low (CPOL = 0). A new conversion cycle can be triggered using the CS signal without having to generate any serial clock pulses as shown in Figure 12. If SCK is maintained at a low logic level, after the end of a conversion cycle, a new conversion operation can be triggered by pulling CS low and then high. When CS is pulled low (CS = LOW), SDO will
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD clk4 SLP DATA OUTPUT CONVERT
24602 F07
clk15
clk16
clk17
SDI
Figure 7. Idle-High (CPOL = 1) Clock Operation Example. A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD clk4 clk14 SLP DATA OUTPUT CONVERT
24602 F08
clk15
clk16
SDI
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
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LTC2460/LTC2462 APPLICATIONS INFORMATION
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD clk4 SLP DATA OUTPUT CONVERT
24602 F09
clk14
clk15
clk16
SDI
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
CS
SD0
D15
D14
D13
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD clk4 SLP CONVERT
24602 F10
SDI
DATA OUTPUT
Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example
CS
SD0
D15
D14
D13
SCK clk1 EN1 CONVERT NAP clk2 EN2 clk3 SPD SLP CONVERT
24602 F11
SDI
DATA OUTPUT
Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example
CS
SD0 SDI = DON'T CARE SCK = LOW
D15
CONVERT
NAP
DATA OUTPUT
CONVERT
24602 F12
Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
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LTC2460/LTC2462 APPLICATIONS INFORMATION
output the sign (D15) of the result of the just completed conversion. While a low logic level is maintained at SCK pin and CS is subsequently pulled high (CS = HIGH) the remaining 15 bits of the result (D14:D0) are discarded and a new conversion cycle starts. Following the aborted I/O, additional clock pulses in the CONVERT state are acceptable, but excessive signal transitions on SCK can potentially create noise on the ADC during the conversion, and thus may negatively influence the conversion accuracy. 2-Wire Operation The 2-wire operation modes, while reducing the number of required control signals, should be used only if the LTC2460/LTC2462 low power sleep capability is not required. In addition the option to abort serial data transfers is no longer available. Hardwire CS to GND for 2-wire operation. For the LTC2460, tie SDI LOW for 60Hz output rate and HIGH for 30Hz output rate, for the LTC2462 tie SDI low. Figure 13 shows a 2-wire operation sequence which uses an idle-high (CPOL = 1) serial clock signal. The conversion status can be monitored at the SDO output. Following a conversion cycle, the ADC enters the data output state and the SDO output transitions from HIGH to LOW. Subsequently 16 clock pulses are applied to the SCK input in order to serially shift the 16 bit result. Finally, the 17th clock pulse is applied to the SCK input in order to trigger a new conversion cycle. Figure 14 shows a 2-wire operation sequence which uses an idle-low (CPOL = 0) serial clock signal. The conversion status cannot be monitored at the SDO output. Following a conversion cycle, the LTC2460/LTC2462 enters the DATA OUTPUT state. At this moment the SDO pin outputs the sign (D15) of the conversion result. The user must use external timing in order to determine the end of conversion and result availability. Subsequently 16 clock pulses are applied to SCK in order to serially shift the 16-bit result. The 16th clock falling edge triggers a new conversion cycle. For the LTC2460 tie SDI LOW for 60Hz output rate and HIGH for 30Hz output rate.
CS = LOW
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 CONVERT SDI = 0 OR 1 clk2 clk3 clk4 clk15 clk16 clk17 CONVERT
24602 F13
DATA OUTPUT
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
CS = LOW
SD0
D15
D14
D13
D12
D2
D1
D0
SCK clk1 CONVERT SDI = 0 OR 1 clk2 clk3 clk4 clk14 clk15 clk16 CONVERT
24602 F14
DATA OUTPUT
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
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LTC2460/LTC2462 APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY The LTC2460/LTC2462 are designed to minimize the conversion result's sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC - 0.5V may result in additional current leakage from the part. Undershoot and overshoot should also be minimized, particularly while the chip is converting. It is thus beneficial to keep edge rates of about 10ns and limit overshoot and undershoot to less than 0.3V. Noisy external circuitry can potentially impact the output under 2-wire operation. In particular, it is possible to get the LTC2460/LTC2462 into an unknown state if an SCK pulse is missed or noise triggers an extra SCK pulse. In this situation, it is impossible to distinguish SDO = 1 (indicating conversion in progress) from valid "1" data bits. As such, CPOL = 1 is recommended for the 2-wire mode. The user should look for SDO = 0 before reading data, and look for SDO = 1 after reading data. If SDO does not return a "0" within the maximum conversion time (or return a "1" after a full data read), generate 16 SCK pulses to force a new conversion. Driving VCC and GND In relation to the VCC and GND pins, the LTC2460/LTC2462 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1F high quality, ceramic capacitor in parallel with , a 10F low ESR ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC package. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin,
IN+ ILEAK CEQ 0.35pF (TYP)
passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. As shown in Figure 15, REF- is used as the negative reference voltage input to the ADC. This pin can be tied directly to ground or kelvined to sensor ground. In the case where REF- is used as a sense input, it should be bypassed to ground with a 0.1F ceramic capacitor in parallel with a 10F low ESR ceramic capacitor. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have two distinct connections: the first to the decoupling capacitors described above, and the second to the ground return for the power supply voltage source. REFOUT and COMP The on chip 1.25V reference is internally tied to the converter's reference input and is output to the REFOUT
INTERNAL REFERENCE ILEAK REFOUT ILEAK
VCC
RSW 15k (TYP)
VCC ILEAK
RSW 15k (TYP)
VCC ILEAK IN- ILEAK
RSW 15k (TYP)
VCC ILEAK REF- ILEAK
RSW 15k (TYP)
24602 F15
Figure 15. LTC2460/LTC2462 Analog Input/Reference Equivalent Circuit
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LTC2460/LTC2462 APPLICATIONS INFORMATION
pin. A 0.1F capacitor should be placed on the REFOUT pin. It is possible to reduce this capacitor, but the transition noise increases. A 0.1F capacitor should also be placed on the COMP pin. This pin is tied to an internal point in the reference and is used for stability. In order for the reference to remain stable the capacitor placed on the COMP pin must be greater than or equal to the capacitor tied to the REFOUT pin. The REFOUT pin cannot be overridden by an external voltage. If a reference voltage greater than 1.25V is required, the LTC2450/LTC2452 should be used. Depending on the size of the capacitors tied to the REFOUT and COMP pins, the internal reference has a corresponding start up time. This start up time is typically 12ms when 0.1F capacitors are used. At initial power up, the first conversion result can be aborted or ignored. At the completion of this first conversion, the reference has settled and all subsequent conversions are valid. If the reference is put to sleep (program SLP = 1 and CS = 1) the reference is powered down after the next conversion. This conversion result is valid. On CS falling edge, the reference is powered up. In order to ensure the reference output has settled before the next conversion, the power up time can be extended by delaying the data read 12ms after the falling edge of CS. Once all 16 bits are read from the device or CS is brought HIGH, the next conversion automatically begins. In the default operation, the reference remains powered up at the conclusion of the conversion cycle. Driving VIN+ and VIN- The input drive requirements can best be analyzed using the equivalent circuit of Figure 16. The input signal VSIG is connected to the ADC input pins (IN+ and IN-) through an equivalent source resistance RS. This resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. Optional input capacitors CIN are also connected to the ADC input pins. This capacitor is placed in parallel with the ADC input parasitic capacitance CPAR. Depending on the PCB . layout, CPAR has typical values between 2pF and 15pF In addition, the equivalent circuit of Figure 16 includes the converter equivalent internal resistor RSW and sampling capacitor CEQ.
IN (LTC2460) RS SIG+ IN+ (LTC2462) CIN CPAR VCC RS SIG- IN- (LTC2462) CIN CPAR ILEAK ILEAK VCC ILEAK ILEAK RSW 15k (TYP) CEQ 0.35pF (TYP) RSW 15k (TYP) CEQ 0.35pF (TYP)
+ -
ICONV
+ -
ICONV
24602 F16
Figure 16. LTC2460/LTC2462 Input Drive Equivalent Circuit
There are some immediate trade-offs in RS and CIN without needing a full circuit analysis. Increasing RS and CIN can give the following benefits: 1) Due to the LTC2460/LTC2462's input sampling algorithm, the input current drawn by either VIN+ or VIN- over a conversion cycle is typically 50nA. A high RS * CIN attenuates the high frequency components of the input current, and RS values up to 1k result in <1LSB error. 2) The bandwidth from VSIG is reduced at the input pins (IN+, IN- or IN). This bandwidth reduction isolates the ADC from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) Switching transients generated by the ADC are attenuated before they go back to the signal source. 4) A large CIN gives a better AC ground at the input pins, helping reduce reflections back to the signal source. 5) Increasing RS protects the ADC by limiting the current during an outside-the-rails fault condition.
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LTC2460/LTC2462 APPLICATIONS INFORMATION
There is a limit to how large RS * CIN should be for a given application. Increasing RS beyond a given point increases the voltage drop across RS due to the input current, to the point that significant measurement errors exist. Additionally, for some applications, increasing the RS * CIN product too much may unacceptably attenuate the signal at frequencies of interest. For most applications, it is desirable to implement CIN as a high-quality 0.1F ceramic capacitor and RS 1k. This capacitor should be located as close as possible to the actual VIN package pin. Furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. In the case of a 2-wire sensor that is not remotely grounded, it is desirable to split RS and place series resistors in the ADC input line as well as in the sensor ground return line, which should be tied to the ADC GND pin using a star connection topology. Figure 17 shows the measured LTC2462 INL vs Input Voltage as a function of RS value with an input capacitor . CIN = 0.1F In some cases, RS can be increased above these guidelines. The input current is zero when the ADC is either in sleep or I/O modes. Thus, if the time constant of the input RC circuit = RS * CIN, is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. These considerations need to be balanced out by the input signal bandwidth. The 3dB bandwidth 1/(2RSCIN). Finally, if the recommended choice for CIN is unacceptable for the user's specific application, an alternate strategy is to eliminate CIN and minimize CPAR and RS. In practical terms, this configuration corresponds to a low impedance sensor directly connected to the ADC through minimum length traces. Actual applications include current measurements through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so on. The resultant INL vs VIN is shown in Figure 18. The measurements of Figure 18 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum width input trace of about 1 inch length. Signal Bandwidth, Transition Noise and Noise Equivalent Input Bandwidth The LTC2460/LTC2462 include a sinc1 type digital filter with the first notch located at f0 = 60Hz. As such, the 3dB input signal bandwidth is 26.54Hz. The calculated LTC2460/LTC2462 input signal attenuation vs frequency over a wide frequency range is shown in Figure 19. The calculated LTC2460/LTC2462 input signal attenuation vs frequency at low frequencies is shown in Figure 20. The converter noise level is about 2.2VRMS and can be modeled by a white noise source connected at the input of a noise-free converter. On a related note, the LTC2462 uses two separate A/D converters to digitize the positive and negative inputs. Each of these A/D converters has 2.2VRMS transition noise. If one of the input voltages is within this small transition noise band, then the output will fluctuate one bit, regardless of the value of the other input voltage. If both of the input voltages are within their transition noise bands, the output can fluctuate 2 bits. For a simple system noise analysis, the VIN drive circuit can be modeled as a single-pole equivalent circuit characterized by a pole location fi and a noise spectral density ni. If the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than fi, then the total noise contribution of the external drive circuit would be: Vn = ni / 2 * fi Then, the total system noise level can be estimated as the square root of the sum of (Vn2) and the square of the LTC2460/LTC2462 noise floor (~2.2V2).
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LTC2460/LTC2462 APPLICATIONS INFORMATION
3 2 RS = 10k 1 INL (LSB) 0 RS = 0k -1 -2 -3 -1.25 INL (LSB) RS = 1k 1 RS = 0k 0 RS = 1k -1 -2 -3 -1.25 CIN = 0.1F VCC = 5V TA = 25C 3 2 RS = 10k CIN = 0 VCC = 5V TA = 25C
0.25 0.75 -0.75 -0.25 DIFFERENTIAL INPUT VOLTAGE (V)
1.25
0.25 0.75 -0.75 -0.25 DIFFERENTIAL INPUT VOLTAGE (V)
1.25
24602 F17
24602 F18
Figure 17. Measured INL vs Input Voltage
Figure 18. Measured INL vs Input Voltage
0 INPUT SIGNAL ATTENUATIOIN (dB) 0 2.5 5.0 7.5 1.00 1.25 1.50 INPUT SIGNAL ATTENUATION (dB)
0 -5 -10 -15 -20 -25 -30 -35 -40 -45
-20
-40
-60
-80
-100 INPUT SIGNAL FREQUENCY (MHz)
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-50
0
60 120 180 240 300 360 420 480 540 600 INPUT SIGNAL FREQUENCY (Hz)
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Figure 19. LTC2462 Input Signal Attentuation vs Frequency
Figure 20. LTC2462 Input Signal Attenuation vs Frequency (Low Frequencies)
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LTC2460/LTC2462 PACKAGE DESCRIPTION
DD Package 12-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
R = 0.115 TYP 7 0.70 0.05 0.40 0.10 12
3.50 0.05 2.10 0.05
2.38 0.05 1.65 0.05
PACKAGE OUTLINE
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6)
2.38 0.10 1.65 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 45 CHAMFER
6 0.25 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 - 0.05 2.25 REF 0.200 REF 0.75 0.05
1
0.23 0.05 0.45 BSC
(DD12) DFN 0106 REV A
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
MS Package 12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev O)
4.039 0.102 (.159 .004) (NOTE 3)
12 11 10 9 8 7
0.889 (.035
0.127 .005)
0.406 0.076 (.016 .003) REF
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136)
GAUGE PLANE
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
0.18 (.007)
0.53 0.152 (.021 .006)
DETAIL "A" SEATING PLANE
123456 1.10 (.043) MAX
0.86 (.034) REF
RECOMMENDED SOLDER PAD LAYOUT
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 - 0.38 (.009 - .015) TYP
0.650 (.0256) BSC
0.1016 (.004
0.0508 .002)
MSOP (MS12) 1107 REV O
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2460/LTC2462 TYPICAL APPLICATION
10F VCC V+ 0.1F CS SCK SDO 1 1k IN+ IN- 1k 0.1F 9 0.1F 0.1F 10 IN+ LTC2462 IN- COMP REF- GND 2 0.1F
24602 TA02
0.1F
VCC
1F
1 10V 2 5V
C
12 CS SCK SDO SDI 3 5 6 4
U1*
REFOUT VCC
6 CS 4 SCK/SCL 7 MOSI/SDA 5 MISO/SDO GND GND GND 3 8 13
8
7, 11
RELATED PARTS
PART NUMBER LTC1860/LTC1861 LTC1860L/LTC1861L LTC1864/LTC1865 LTC1864L/LTC1865L LTC2360 LTC2440 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC6241 LTC2450 LTC2450-1 LTC2451 LTC2452 LTC2453 DESCRIPTION 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC 12-Bit, 100ksps SAR ADC 24-Bit No Latency TM ADC 16-Bit, Differential Input, No Latency ADC, with PGA, Temp. Sensor, SPI 16-Bit, Differential Input, No Latency ADC, with PGA, Temp. Sensor, I2C 16-Bit, Differential Input, No Latency ADC, SPI 16-Bit, Differential Input, No Latency ADC, I2C 24-Bit, Differential Input, No Latency ADC, SPI with Temp. Sensor 24-Bit, Differential Input, No Latency ADC, I2C with Temp. Sensor Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input Range Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input Range Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C, 0V to 5.5V Input Range Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI, 5.5V Input Range Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C, 5.5V Input Range COMMENTS 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages 200nVRMS Noise, 4kHz Output Rate, 15ppm INL Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package 550nVP-P Noise, 125V Offset Max 2 LSB INL, 50nA Sleep current, Tiny 2mm x 2mm DFN-6 Package, 30Hz Output Rate 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 60Hz Output Rate 2 LSB INL, 50nA Sleep Current, Tiny 3mm x 2mm DFN-8 or TSOT Package, Programmable 30Hz/60Hz Output Rates 2 LSB INL, 50nA Sleep Current, Tiny 3mm x 2mm DFN-8 or TSOT Package 2 LSB INL, 50nA Sleep Current, Tiny 3mm x 2mm DFN-8 or TSOT Package
No Latency is a trademark of Linear Technology Corporation.
24602f
20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0409 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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